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ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
14 years 10 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
16 years 1 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
HICSS
2003
IEEE
122views Biometrics» more  HICSS 2003»
16 years 16 hour ago
A Three-Layer Architecture for E-Contract Enforcement in an E-Service Environment
In an e-service environment, contracts are important for attaining business process interoperability and enforcing their proper enactment. An e-contract is the computerized facili...
Dickson K. W. Chiu, Shing-Chi Cheung, Sven Till
METRICS
2003
IEEE
16 years 1 hour ago
Using Service Utilization Metrics to Assess the Structure of Product Line Architectures
Metrics have long been used to measure and evaluate software products and processes. Many metrics have been developed that have lead to different degrees of success. Software arch...
André van der Hoek, Ebru Dincel, Nenad Medv...
SEKE
2009
Springer
15 years 11 months ago
Collaborative Development of System Architecture - a Tool for Coping with Inconsistency
Very large systems have an architecture that is designed to allow them to evolve through a long life. Such systems are developed by teams of architects. One of the first things t...
Peter Henderson, Matthew J. Henderson