Sciweavers

6819 search results - page 254 / 1364
» Process Reuse Architecture
Sort
View
181
Voted
IJCSA
2008
100views more  IJCSA 2008»
15 years 6 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
15 years 11 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
APPINF
2003
15 years 8 months ago
Comparing the Optimal Performance of Multiprocessor Architectures
Consider a parallel program with n processes and a synchronization granularity z. Consider also two multiprocessors: a multiprocessor with q processors and run-time reallocation o...
Lars Lundberg, Kamilla Klonowska, Magnus Broberg, ...
ICDE
2003
IEEE
138views Database» more  ICDE 2003»
16 years 8 months ago
Using State Modules for Adaptive Query Processing
We present a query architecture in which join operators are decomposed into their constituent data structures (State Modules, or SteMs), and dataflow among these SteMs is managed ...
Vijayshankar Raman, Amol Deshpande, Joseph M. Hell...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
16 years 8 days ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...