6819 search results - page 1142 / 1364 » Process Reuse Architecture |
159
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
159
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
161
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
124
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the ...
164
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...