6819 search results - page 1141 / 1364 » Process Reuse Architecture |
181
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
152
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
139
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
This paper presents an optimal procrastinating voltage scheduling (OP-DVS) for hard real-time systems using stochastic workload information. Algorithms are presented for both sing...
159
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
188
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...