6819 search results - page 1122 / 1364 » Process Reuse Architecture |
184
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ISCA
1998
IEEE
15 years 10 months ago
1998
IEEE
Commercial applications such as databases and Web servers constitute the largest and fastest-growing segment of the market for multiprocessor servers. Ongoing innovations in disk ...
170
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ARVLSI
1997
IEEE
15 years 10 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
179
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FC
1997
Springer
15 years 10 months ago
1997
Springer
Abstract. SPEED is a private key block cipher. It supports three variable parameters: (1) data length — the length of a plaintext/ciphertext of SPEED can be 64, 128 or 256 bits. ...
167
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...
166
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ICFP
2007
ACM
15 years 10 months ago
2007
ACM
In this paper we introduce the iTask system: a set of combinators to specify work flows in a pure functional language at a very high level of abstraction. Work flow systems are au...