6819 search results - page 1115 / 1364 » Process Reuse Architecture |
173
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ISPASS
2008
IEEE
16 years 28 days ago
2008
IEEE
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
164
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MICRO
2008
IEEE
16 years 28 days ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
175
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CODES
2007
IEEE
16 years 26 days ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
186
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COMSWARE
2007
IEEE
16 years 26 days ago
2007
IEEE
—Sensor networks represent a new frontier in technology that holds the promise of unprecedented levels of autonomy in the execution of complex dynamic missions by harnessing the ...
176
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ISVLSI
2007
IEEE
16 years 24 days ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...