20 search results - page 3 / 4 » Procedure Merging with Instruction Caches |
129
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ISCA
2006
IEEE
15 years 12 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
164
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CSREAESA
2006
15 years 7 months ago
2006
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
143
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CASES
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a new register assignment heuristic for procedures in SSA Form, whose interference graphs are chordal; the heuristic is called optimistic chordal coloring (OCC...
155
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MICRO
1998
IEEE
15 years 10 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
189
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ECOOP
1995
Springer
15 years 9 months ago
1995
Springer
Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve p...