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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
16 years 1 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
GPC
2009
Springer
16 years 1 months ago
Efficient Parallelized Network Coding for P2P File Sharing Applications
In this paper, we investigate parallel implementation techniques for network coding to enhance the performance of Peer-to-Peer (P2P) file sharing applications. It is known that net...
Karam Park, Joon-Sang Park, Won Woo Ro
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
16 years 28 days ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
RSP
2008
IEEE
120views Control Systems» more  RSP 2008»
16 years 27 days ago
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rende...
Mateusz Majer, Stefan Wildermann, Josef Angermeier...
CEC
2007
IEEE
16 years 26 days ago
Evolutionary optimization of parameters for distributed virtual environments
—In a distributed virtual environment interest management schemes attempt to ensure virtual world objects exchange messages only if they are interacting. This provides an opportu...
Simon E. Parkin, Peter Andras, Graham Morgan
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