Sciweavers

13026 search results - page 2165 / 2606
» Probabilistic Relational Models
Sort
View
CASES
2006
ACM
16 years 26 days ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
CF
2006
ACM
16 years 26 days ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
16 years 13 days ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
IUI
2005
ACM
16 years 13 days ago
ScentHighlights: highlighting conceptually-related sentences during reading
Researchers have noticed that readers are increasingly skimming instead of reading in depth. Skimming also occur in re-reading activities, where the goal is to recall specific top...
Ed Huai-hsin Chi, Lichan Hong, Michelle Gumbrecht,...
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
16 years 13 days ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
« Prev « First page 2165 / 2606 Last » Next »