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139
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
204
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DATE
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
175
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ISPD
1997
ACM
15 years 11 months ago
1997
ACM
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
152
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GECCO
2006
Springer
15 years 10 months ago
2006
Springer
We present an evolutionary methodology that explores the evolution of network topology when a uniform growth of the network traffic is considered. The network redesign problem is ...
202
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ASPDAC
2008
ACM
15 years 8 months ago
2008
ACM
Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve...