We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Abstract: Starting from the Rational Unified Process RUP and the ARIS life cycle model the ARIS Unified Information System Development Process AUP is designed. Similar as the RUP i...
This paper makes three significant extensions to a noisy channel speller designed for standard written text to target the challenging domain of search queries. First, the noisy ch...
Jianfeng Gao, Xiaolong Li, Daniel Micol, Chris Qui...
For decades we have been using Chomsky's generative system of grammars, particularly context-free grammars (CFGs) and regular expressions (REs), to express the syntax of prog...
In this paper, we develop a new language construct to address one of the pitfalls of parallel programming: precise handling of events across parallel components. The construct, te...
William Thies, Michal Karczmarek, Janis Sermulins,...