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IPPS
2005
IEEE
16 years 5 days ago
Programming Configurable Multiprocessors
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
Steven A. Guccione
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
16 years 5 days ago
Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
Valentin Gies, Thierry M. Bernard, Alain Mé...
LICS
2005
IEEE
16 years 4 days ago
Generalizing Parametricity Using Information-flow
Run-time type analysis allows programmers to easily and concisely define operations based upon type structure, such as serialization, iterators, and structural equality. However,...
Geoffrey Washburn, Stephanie Weirich
MSE
2005
IEEE
150views Hardware» more  MSE 2005»
16 years 4 days ago
A Cohesive FPGA-Based System-on-Chip Design Curriculum
A graduate-level computer engineering course sequence at the OGI School of Science and Engineering teaches state-of-the-art digital system design practices and system-on-chip desi...
John D. Lynch, Daniel Hammerstrom, Roy Kravitz
RSP
2005
IEEE
107views Control Systems» more  RSP 2005»
16 years 4 days ago
Rapid Prototyping of Embedded Software Using Selective Formalism
Our software synthesis tool, CSP++, generates C++ source code from verifiable CSPm specifications, and includes a framework for runtime execution. Our technique of selective for...
John D. Carter, Ming Xu, William B. Gardner