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» Predictable performance in SMT processors
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MICRO
2002
IEEE
118views Hardware» more  MICRO 2002»
15 years 11 months ago
Exploiting data-width locality to increase superscalar execution bandwidth
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
Gabriel H. Loh
MICRO
1998
IEEE
92views Hardware» more  MICRO 1998»
15 years 10 months ago
Predictive Techniques for Aggressive Load Speculation
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
Glenn Reinman, Brad Calder
IEEEPACT
2000
IEEE
15 years 10 months ago
The Effect of Code Reordering on Branch Prediction
Branch prediction accuracy is a very important factor for superscalarprocessor performance. The ability topredict the outcome of a branch allows the processor to effectively use a...
Alex Ramírez, Josep-Lluis Larriba-Pey, Mate...
RTAS
2008
IEEE
16 years 11 days ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
ISORC
2011
IEEE
14 years 9 months ago
A Time-Predictable Object Cache
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...
Martin Schoeberl