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TC
2011
15 years 24 days ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
EUROSYS
2007
ACM
16 years 3 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
IISWC
2009
IEEE
16 years 1 months ago
A communication characterisation of Splash-2 and Parsec
Recent benchmark suite releases such as Parsec specifically utilise the tightly coupled cores available in chipmultiprocessors to allow the use of newer, high performance, models ...
Nick Barrow-Williams, Christian Fensch, Simon Moor...
DAC
2001
ACM
16 years 7 months ago
Hypermedia-Aided Design
Recently, the Internet revolutionized many activities from entertainment to marketing and business. Two key underlying Internet technologies, efficient data delivery and hypertext...
Darko Kirovski, Milenko Drinic, Miodrag Potkonjak
EKAW
2008
Springer
15 years 8 months ago
Principles for Knowledge Engineering on the Web
With the advent of the Web and the efforts towards a Semantic Web the nature of knowledge engineering has changed drastically. In this position paper we propose four principles fo...
Guus Schreiber