426 search results - page 78 / 86 » Power-Sensitive Multithreaded Architecture |
290
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SASP
2009
IEEE
16 years 17 days ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
135
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IEEEPACT
2008
IEEE
16 years 7 days ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
157
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IPCCC
2007
IEEE
16 years 3 days ago
2007
IEEE
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
165
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ICS
2007
Tsinghua U.
15 years 12 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
171
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IPPS
2006
IEEE
15 years 12 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...