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IESS
2007
Springer
165views Hardware» more  IESS 2007»
16 years 7 days ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
15 years 10 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
LCPC
2005
Springer
15 years 11 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
ICPP
1991
IEEE
15 years 9 months ago
B-SYS: A 470-Processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
Richard Hughey, Daniel P. Lopresti
DSD
2007
IEEE
136views Hardware» more  DSD 2007»
15 years 6 months ago
Error-Aware Design
The universal underlying assumption made today is that Systems on chip must maintain 100% correctness regardless of the application. This work advocates the concept that some appl...
Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Dja...