Sciweavers

228 search results - page 14 / 46
» Power management in external memory using PA-CDRAM
Sort
View
DSD
2004
IEEE
97views Hardware» more  DSD 2004»
15 years 9 months ago
Scene Management Models and Overlap Tests for Tile-Based Rendering
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassil...
JIIS
2002
99views more  JIIS 2002»
15 years 5 months ago
Efficient Management of Persistent Knowledge
Although computer speed has steadily increased and memory is getting cheaper, the need for storage managers to deal efficiently with applications that cannot be held into main memo...
Dimitris G. Kapopoulos, Michael Hatzopoulos, Panag...
ISVLSI
2003
IEEE
147views VLSI» more  ISVLSI 2003»
15 years 11 months ago
Automated Dynamic Memory Data Type Implementation Exploration and Optimization
The behavior of many algorithms is heavily determined by the input data. Furthermore, this often means that multiple and completely different execution paths can be followed, also...
Marc Leeman, Chantal Ykman-Couvreur, David Atienza...
WMPI
2004
ACM
15 years 11 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
ASPLOS
2008
ACM
15 years 8 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...