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ISPASS
2007
IEEE
16 years 13 days ago
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
W. Lloyd Bircher, Lizy K. John
CODES
2005
IEEE
15 years 11 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
CODES
2004
IEEE
15 years 10 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
CODES
2003
IEEE
15 years 11 months ago
A low power scheduler using game theory
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
N. Ranganathan, Ashok K. Murugavel
HIPEAC
2005
Springer
15 years 11 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli