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CODES
2006
IEEE
16 years 20 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
CODES
2006
IEEE
16 years 20 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
HICSS
2003
IEEE
151views Biometrics» more  HICSS 2003»
15 years 12 months ago
A Simple GSPN for Modeling Common Mode Failures in Critical Infrastructures
It is now apparent that our nation’s infrastructures and essential utilities have been optimized for reliability in benign operating environments. As such, they are susceptible ...
Axel W. Krings, Paul W. Oman
PLDI
2003
ACM
15 years 12 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
CASES
2007
ACM
15 years 10 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov