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VLSI
2005
Springer
16 years 18 hour ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
CASES
2003
ACM
15 years 11 months ago
Architectural optimizations for low-power, real-time speech recognition
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
CHI
2006
ACM
16 years 7 months ago
Fly: an organic presentation tool
In this paper, we present Fly, a prototype presentation system that adds a visual structure to presentations. Current presentation software, like PowerPoint, structure slides in a...
David Holman, Predrag Stojadinovic, Thorsten Karre...
ISSRE
2008
IEEE
16 years 28 days ago
Using Fault Modeling in Safety Cases
For many safety-critical systems a safety case is built as part of the certification or acceptance process. The safety case assembles evidence to justify that the design and imple...
Robyn R. Lutz, Ann Patterson-Hine
ISORC
2007
IEEE
16 years 25 days ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner