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TCAD
2011
15 years 1 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
APN
2008
Springer
15 years 8 months ago
A Monitoring Toolset for Paose
Abstract Paose (Petri net-based Agent-Oriented Software Engineering) combines the paradigm of AOSE (Agent-Oriented Software Engineering, see [10]) with the expressive power of Petr...
Lawrence Cabac, Till Dörges, Heiko Rölke
ISPASS
2009
IEEE
16 years 1 months ago
Differentiating the roles of IR measurement and simulation for power and temperature-aware design
In temperature-aware design, the presence or absence of a heatsink fundamentally changes the thermal behavior with important design implications. In recent years, chip-level infra...
Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Rob...
LCTRTS
2007
Springer
16 years 15 days ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
CASES
2001
ACM
15 years 10 months ago
Application specific architectures: a recipe for fast, flexible and power efficient designs
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
Christopher T. Weaver, Rajeev Krishna, Lisa Wu, To...