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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 19 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
16 years 17 days ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
IPPS
2005
IEEE
16 years 6 days ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...
ANCS
2005
ACM
16 years 5 days ago
SSA: a power and memory efficient scheme to multi-match packet classification
New network applications like intrusion detection systems and packet-level accounting require multi-match packet classification, where all matching filters need to be reported. Te...
Fang Yu, T. V. Lakshman, Martin Austin Motoyama, R...
CORR
2010
Springer
162views Education» more  CORR 2010»
15 years 6 months ago
Power Allocation Games in Wireless Networks of Multi-antenna Terminals
We consider wireless networks that can be modeled by multiple access channels in which all the terminals are equipped with multiple antennas. The propagation model used to account...
Elena Veronica Belmega, Samson Lasaulce, Mé...