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HIPEAC
2009
Springer
16 years 1 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
CASES
2006
ACM
16 years 16 days ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
CN
2007
168views more  CN 2007»
15 years 6 months ago
A MAC layer power management scheme for efficient energy delay tradeoff in a WLAN
— Energy efficient operation is of paramount importance for battery-powered wireless nodes. In an effort to conserve energy, standard protocols for WLANs have the provision for w...
Mahasweta Sarkar, Rene L. Cruz
ASPLOS
2008
ACM
15 years 8 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
IPCCC
2007
IEEE
16 years 26 days ago
A Hybrid Disk-Aware Spin-Down Algorithm with I/O Subsystem Support
To offset the significant power demands of hard disk drives in computer systems, drives are typically powered down during idle periods. This saves power, but accelerates duty cyc...
Timothy Bisson, Scott A. Brandt, Darrell D. E. Lon...