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VTC
2007
IEEE
146views Communications» more  VTC 2007»
16 years 21 days ago
Orthogonal STBC in General Nakagami-m Fading Channels: BER Analysis and Optimal Power Allocation
Abstract— We analyze the performance of multiple-input multiple-output (MIMO) systems employing orthogonal space-time block codes (STBC) in general Nakagami-m fading channels wit...
Andreas Müller, Joachim Speidel
ISCAS
2006
IEEE
131views Hardware» more  ISCAS 2006»
16 years 14 days ago
Static generator model for analog power flow computation
—Accurate analog models of power system components are required in order to realize an analog computation engine for power systems. Analog computation is an area of continued int...
Aaron St. Leger, Chika O. Nwankpa
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
15 years 12 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 11 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
CC
2002
Springer
131views System Software» more  CC 2002»
15 years 6 months ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal