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ISCAS
2007
IEEE
75views Hardware» more  ISCAS 2007»
16 years 22 days ago
State-Space Analysis of Power Complementary Analog Filters
Abstract— This paper presents a new analysis of power complementary analog filters using the state-space representation. Our analysis is based on the bounded-real Riccati equati...
Shunsuke Koshita, Masahide Abe, Masayuki Kawamata
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
16 years 13 days ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
16 years 12 days ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
15 years 10 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
EVOW
1999
Springer
15 years 10 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...