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ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
16 years 21 days ago
Low-Power Circuits for Brain-Machine Interfaces
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...
Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjami...
TC
2002
15 years 6 months ago
Dynamic Power Management for Nonstationary Service Requests
Dynamic Power Management (DPM) is a design methodology aiming at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. The eff...
Eui-Young Chung, Luca Benini, Alessandro Bogliolo,...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
16 years 14 days ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
CISS
2008
IEEE
15 years 8 months ago
Diversity-multiplexing gain tradeoff with peak to average power ratio constraints
Zheng and Tse have shown that over a quasi-static channel, there exists a fundamental tradeoff, known as the diversity-multiplexing gain (D-MG) tradeoff. In a realistic system, to ...
Chung-Pi Lee, Hsuan-Jung Su