121 search results - page 4 / 25 » Power distribution techniques for dual VDD circuits |
152
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
140
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IWSOC
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
153
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ISCAS
2006
IEEE
16 years 46 min ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
159
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
174
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DAC
1999
ACM
15 years 10 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...