157 search results - page 14 / 32 » Power and performance tradeoffs using various caching strate... |
232
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HPCA
2011
IEEE
14 years 9 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
138
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
— This paper evaluates various instruction- and data-cache organizations in terms of performance, power, energy and area on a suitably selected biomedical benchmark suite. The be...
166
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ISCA
1997
IEEE
15 years 10 months ago
1997
IEEE
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
157
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IPPS
2007
IEEE
16 years 11 days ago
2007
IEEE
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
141
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CODES
2000
IEEE
15 years 10 months ago
2000
IEEE
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...