173 search results - page 14 / 35 » Power Reducing Techniques for Clocked CMOS PLAs |
152
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DATE
2009
IEEE
16 years 24 days ago
2009
IEEE
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
148
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
124
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ICCD
2004
IEEE
16 years 2 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-ef...
169
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
150
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ISCAS
2007
IEEE
16 years 9 days ago
2007
IEEE
— Domino circuits are used to achieve higher system performance than static CMOS techniques. This work briefly surveys domino keeper designs for high fan-in domino circuits. A ne...