1238 search results - page 201 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
174
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FPL
2010
Springer
15 years 4 months ago
2010
Springer
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
167
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
148
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CGO
2010
IEEE
15 years 10 months ago
2010
IEEE
Shadow value tools use metadata to track properties of application data at the granularity of individual machine instructions. These tools provide effective means of monitoring an...
154
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TVCG
2010
15 years 26 days ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
195
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APCSAC
2007
IEEE
15 years 10 months ago
2007
IEEE
Many years of CMOS technology scaling have resulted in increased power densities and higher core temperatures. Power and temperature concerns are now considered to be a primary cha...