1238 search results - page 199 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
165
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EUROPAR
2009
Springer
16 years 23 days ago
2009
Springer
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
186
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ISHPC
1999
Springer
15 years 10 months ago
1999
Springer
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
151
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
155
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
173
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ICS
2009
Tsinghua U.
15 years 10 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...