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IPPS
2005
IEEE
15 years 11 months ago
Programming Configurable Multiprocessors
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
Steven A. Guccione
ARITH
1999
IEEE
15 years 10 months ago
Multiplications of Floating Point Expansions
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of an...
Marc Daumas
RECOSOC
2007
116views Hardware» more  RECOSOC 2007»
15 years 7 months ago
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking
Code Compression has been shown to be efficient in minimizing the memory requirements for embedded systems as well as in power consumption reduction and performance improvement. I...
Eduardo Wanderley Netto, Reouven Elbaz, Lionel Tor...
MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
15 years 6 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
CODES
2007
IEEE
16 years 16 days ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...