Sciweavers

1238 search results - page 178 / 248
» Power Efficient Processor Architecture and The Cell Processo...
Sort
View
DAC
2005
ACM
16 years 7 months ago
Fine-grained application source code profiling for ASIP design
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
ISCAS
2008
IEEE
144views Hardware» more  ISCAS 2008»
16 years 23 days ago
A novel VLSI iterative divider architecture for fast quotient generation
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li
ISCAPDCS
2007
15 years 7 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
ISCC
2005
IEEE
119views Communications» more  ISCC 2005»
15 years 12 months ago
A Systematic Approach to Building High Performance Software-Based CRC Generators
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
Michael E. Kounavis, Frank L. Berry
DAC
2005
ACM
15 years 8 months ago
Modular domain-specific implementation and exploration framework for embedded software platforms
This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular applic...
Christian Sauer, Matthias Gries, Sören Sonnta...