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IJCSA
2008
100views more  IJCSA 2008»
15 years 6 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
DSN
2006
IEEE
15 years 10 months ago
Efficient High Hamming Distance CRCs for Embedded Networks
Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techn...
Justin Ray, Philip Koopman
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 22 days ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
ICASSP
2011
IEEE
14 years 10 months ago
Reconfigurable decoder architectures for Raptor codes
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes compo...
Hady Zeineddine, Mohammad M. Mansour
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
16 years 24 days ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks