1238 search results - page 160 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
164
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CHES
2009
Springer
16 years 7 months ago
2009
Springer
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
211
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ICIP
2009
IEEE
15 years 4 months ago
2009
IEEE
We investigate energy allocation strategies in image sensor networks for the purpose of maximizing the network operational lifetime. For the application scenarios that we consider...
168
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
171
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HPCA
1995
IEEE
15 years 10 months ago
1995
IEEE
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
146
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...