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ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
16 years 12 days ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 10 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
16 years 26 days ago
Resilient Dynamic Power Management under Uncertainty
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
Hwisung Jung, Massoud Pedram
DAC
1999
ACM
16 years 7 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
DSN
2009
IEEE
16 years 1 months ago
Power supply induced common cause faults-experimental assessment of potential countermeasures
Fault-tolerant architectures based on physical replication of components are vulnerable to faults that cause the same effect in all replica. Short outages in a power supply shared...
Peter Tummeltshammer, Andreas Steininger