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SAMOS
2005
Springer
15 years 12 months ago
Automatic ADL-Based Assembler Generation for ASIP Programming Support
Abstract. Systems-on-Chip (SoCs) may be built upon general purpose CPUs or application-specific instruction-set processors (ASIPs). On the one hand, ASIPs allow a tradeoff betwee...
Leonardo Taglietti, José O. Carlomagno Filh...
WCET
2010
15 years 4 months ago
WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core
To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question o...
Christine Rochange, Armelle Bonenfant, Pascal Sain...
ESTIMEDIA
2009
Springer
16 years 29 days ago
Software parallel CAVLC encoder based on stream processing
—Real-time encoding of high-definition H.264 video is a challenge to current embedded programmable processors. Emerging stream processing methods supported by most GPUs and progr...
Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Z...
SAC
2008
ACM
15 years 5 months ago
Power-efficient and scalable load/store queue design via address compression
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
ANCS
2007
ACM
15 years 10 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos