1238 search results - page 150 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
151
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
174
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MICRO
2008
IEEE
15 years 6 months ago
2008
IEEE
UAL PRIVATE MACHINE ABSTRACTION WOULD ALLOW SOFTWARE POLICIES TO EXPLICITLY MANAGE MICROARCHITECTURE RESOURCES. VPM POLICIES, IMPLEMENTED PRIMARILY IN SOFTWARE, TRANSLATE APPLICATI...
211
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PPAM
2005
Springer
15 years 12 months ago
2005
Springer
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
153
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HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
184
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TCAD
2010
15 years 1 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...