1238 search results - page 149 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
199
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TII
2010
15 years 1 months ago
2010
Abstract--CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable e...
160
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MICRO
2005
IEEE
16 years 4 hour ago
2005
IEEE
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
173
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
As application complexity increases, modern embedded systems have adopted heterogeneous processing elements to enhance the computing capability or to reduce the power consumption. ...
186
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INFORMATICALT
2006
15 years 6 months ago
2006
Matrix transpose in parallel systems typically involves costly all-to-all communications. In this paper, we provide a comparative characterization of various efficient algorithms f...
181
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...