1238 search results - page 143 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
162
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VLSISP
1998
15 years 6 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
152
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ICCD
2002
IEEE
16 years 3 months ago
2002
IEEE
Our goal is to identify the key architectural and design issues related to Sensor Networks (SNs), evaluate the proposed solutions, and to outline the most challenging research dir...
135
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ASPDAC
2006
ACM
16 years 11 days ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
143
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DATE
2007
IEEE
16 years 23 days ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
148
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...