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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 13 days ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
SC
2004
ACM
15 years 12 months ago
Analysis and Performance Results of a Molecular Modeling Application on Merrimac
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. D...
DAC
2011
ACM
14 years 6 months ago
Throughput maximization for periodic real-time systems under the maximal temperature constraint
We study the problem on how to maximize the throughput for a periodic real-time system under the given peak temperature constraint. We assume that different tasks in our system ma...
Huang Huang, Gang Quan, Jeffrey Fan, Meikang Qiu
IISWC
2008
IEEE
16 years 25 days ago
Energy-aware application scheduling on a heterogeneous multi-core system
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
Jian Chen, Lizy Kurian John
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 10 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...