1238 search results - page 135 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
198
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ISCAPDCS
2003
15 years 7 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
178
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FPL
2005
Springer
15 years 12 months ago
2005
Springer
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
178
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TC
2010
15 years 1 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
152
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ICCD
2001
IEEE
16 years 3 months ago
2001
IEEE
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permut...
172
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IPSN
2003
Springer
15 years 11 months ago
2003
Springer
We investigated the tradeoffs between accuracy and battery-energy longevity of acoustic beamforming on disposable sensor nodes subject to varying key parameters: 1) number of micr...