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VTS
2005
IEEE
106views Hardware» more  VTS 2005»
15 years 11 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 11 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
SC
1994
ACM
15 years 10 months ago
The range test: a dependence test for symbolic, non-linear expressions
Most current data dependence tests cannot handle loop bounds or array subscripts that are symbolic, nonlinear expressions e.g. Ani+j, where 0 j n. In this paper, we describe a d...
William Blume, Rudolf Eigenmann
SOCC
2008
IEEE
117views Education» more  SOCC 2008»
16 years 8 days ago
In-situ self-aware adaptive power control system with multi-mode power gating network
An in-situ self-aware adaptive power control (APC) system is presented in this paper. This APC system consists of a voltage sensor, a variable threshold comparator, slack detectio...
Wei-Chih Hsieh, Wei Hwang
ATS
2005
IEEE
139views Hardware» more  ATS 2005»
15 years 11 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy