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FPL
2006
Springer
169views Hardware» more  FPL 2006»
15 years 10 months ago
An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic
An improved FPGA implementation of an electronic cochlea filter is presented. We show that by using decimation, the computations of the electronic cochlea can be reduced. Furtherm...
C. K. Wong, Philip Heng Wai Leong
FPL
2006
Springer
140views Hardware» more  FPL 2006»
15 years 10 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
ARITH
2001
IEEE
15 years 10 months ago
1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features
Ajay Naini, Atul Dhablania, Warren James, Debjit D...