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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
155
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DAGSTUHL
2010
15 years 8 months ago
Model-Based Visualization for Intervention Planning
Computer support for intervention planning is a two-stage process: In a first stage, the relevant segmentation target structures are identified and delineated. In a second stage, ...
Bernhard Preim
STAIRS
2008
143views Education» more  STAIRS 2008»
15 years 8 months ago
Domain-Dependent View of Multiple Robots Path Planning
We study a problem of path planning for a group of robots in this paper. The problem is stated as a finding of spatial-temporal paths through which the robots can go from their ini...
Pavel Surynek
AAAI
2006
15 years 8 months ago
Functional Value Iteration for Decision-Theoretic Planning with General Utility Functions
We study how to find plans that maximize the expected total utility for a given MDP, a planning objective that is important for decision making in high-stakes domains. The optimal...
Yaxin Liu, Sven Koenig
AIPS
2006
15 years 8 months ago
Predictive Planning for Supply Chain Management
Supply chains are ubiquitous in the manufacturing of many complex products. Traditionally, supply chains have been created through the intricate interactions of human representati...
David Pardoe, Peter Stone