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» Pipeline Timing Analysis Using a Trace-Driven Simulator
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CODES
2008
IEEE
15 years 7 months ago
Specification-based compaction of directed tests for functional validation of pipelined processors
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
Heon-Mo Koo, Prabhat Mishra
FASE
2006
Springer
15 years 9 months ago
Formal Simulation and Analysis of the CASH Scheduling Algorithm in Real-Time Maude
This paper describes the application of the Real-Time Maude tool to the formal specification and analysis of the CASH scheduling algorithm and its suggested modifications. The CASH...
Peter Csaba Ölveczky, Marco Caccamo
WSC
2008
15 years 8 months ago
Maximizing the utilization of operating rooms with stochastic times using simulation
This paper addresses a surgery rooms scheduling problem. The problem is modeled as a parallel machine scheduling problem with sequence dependent setup times and an objective of mi...
Jean-Paul M. Arnaout, Sevag Kulbashian
TC
2008
15 years 5 months ago
Self-Adaptive Configuration of Visualization Pipeline Over Wide-Area Networks
Next-generation scientific applications require the capability to visualize large archival data sets or on-going computer simulations of physical and other phenomena over wide-area...
Qishi Wu, Jinzhu Gao, Mengxia Zhu, Nageswara S. V....
DAC
2002
ACM
16 years 6 months ago
Timed compiled-code simulation of embedded software for performance analysis of SOC design
In this paper, a new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of I/O accesses is crucial to performance es...
Jong-Yeol Lee, In-Cheol Park