3 search results - page 1 / 1 » Physical-aware simulated annealing optimization of gate leak... |
182
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DATE
2006
IEEE
16 years 1 days ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
227
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TIM
2010
15 years 21 days ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
169
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...