301 search results - page 33 / 61 » Physical design techniques for optimizing RTA-induced variat... |
160
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DATE
2009
IEEE
16 years 23 days ago
2009
IEEE
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
146
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TCAD
2010
15 years 22 days ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
162
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CODES
2005
IEEE
15 years 11 months ago
2005
IEEE
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
144
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ICCAD
2009
IEEE
15 years 3 months ago
2009
IEEE
Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so ...
156
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...