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ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
16 years 27 days ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
16 years 5 days ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
SLIP
2005
ACM
16 years 5 days ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
BCS
2008
15 years 8 months ago
Overcoming Software Fragility with Interacting Feedback Loops and Reversible Phase Transitions
Programs are fragile for many reasons, including software errors, partial failures, and network problems. One way to make software more robust is to design it from the start as a ...
Peter Van Roy
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
15 years 4 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis