2749 search results - page 243 / 550 » Physical Design of the |
140
click to vote
ASYNC
2003
IEEE
15 years 12 months ago
2003
IEEE
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, t...
181
click to vote
GMP
2000
IEEE
15 years 11 months ago
2000
IEEE
This paper is concerned with “open kernel” geometric modelling systems. It uses industrial needs to identify requirements for the geometric objects of a proposed interface. Th...
147
click to vote
IPPS
2000
IEEE
15 years 11 months ago
2000
IEEE
The work described here introduces a practical and accurate tool for predicting power consumption for FPGA circuits. The utility of the tool is that it enables FPGA circuit designe...
157
click to vote
DAC
1996
ACM
15 years 10 months ago
1996
ACM
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
161
click to vote
ASAP
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...